Just to mention I had to set rules when working with VHDL that might be useful for others.
Cursor made some mistake when writing VHDL code like
Use output signal within an entity
Write the same signal from multiple processes is not allowed.
Once you tell it not to do that again it follows the rules.
The other thing it did that made me laugh is to remove the error message from the tool as a solution. I should have kept that conversation. Probably misunderstood what I was asking for.
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Just one clarification the root issue is not that cursor writes code that uses output signal within an entity. It is that doing that needs to set the file as VHDL 2008 syntax which allows it. The simulation had it broadly set but not the IP. Vivado does not support VHDL-2008 as top level design file so needs a wrapper but I wouldn’t do one just using output locally.
Should be possible to craft a rule to manage the use of VHDL-2008 to and to forward the setting to IP and simulation step.
The update would be to detect if a file needs to be set to VHDL-2008 when it builds the IP but that might be a waste of resources just for that.
I can’t say if having multiple processes drive a single signal would have been supported in VHDL-2008. Might be the same issue but I would avoid.