Feature request for product/service
Cursor IDE
Describe the request
Feature Request: RTL/HDL Design Hierarchy Explorer
Summary
Add a dedicated side panel for visualizing and navigating Verilog/SystemVerilog/VHDL module hierarchies, similar to functionality in Sigasi, DVT Eclipse, Vivado IDE, and Quartus.
Problem Statement
Hardware design engineers working on complex SoC/FPGA/ASIC projects often deal with deep module hierarchies (50-200+ modules). Currently, navigating these requires:
- Manual grep/search for module instantiations
- Jumping between files without context of where you are in the hierarchy
- External EDA tools just for code navigation
Proposed Solution
A “Design Hierarchy” panel in the Explorer sidebar that shows:
Design Hierarchy
└── 
soc_top (top)
├── u_cpu_subsys : cpu_subsystem
│ ├── u_core0 : riscv_core
│ │ ├── u_alu : alu_unit
│ │ ├── u_regfile : register_file
│ │ └── u_decoder : instruction_decoder
│ └── u_cache : l1_cache
├── u_periph_subsys : peripheral_subsystem
│ ├── u_uart0 : uart_controller
│ ├── u_spi_master : spi_master
│ ├── u_i2c0 : i2c_controller
│ └── u_gpio : gpio_controller
├── u_mem_ctrl : ddr_controller
│ └── u_phy : ddr_phy
└── u_noc : network_on_chip
Key Features Requested
| Feature | Description |
|---|---|
| Hierarchy Tree | Expandable/collapsible view of module instantiations |
| Click-to-Navigate | Single click opens module definition file |
| Instance vs Module | Show both instance name and module type |
| Parameter Display | Hover to see parameter overrides |
| Search/Filter | Filter hierarchy by module or instance name |
| Multi-root | Support multiple top-level modules |
| Refresh | Manual/auto refresh when files change |
Supported Languages
- Verilog (.v)
- SystemVerilog (.sv)
- VHDL (.vhd, .vhdl) - optional
Implementation Suggestions
- Leverage existing parsers: Verible (Google’s open-source SV parser), slang, or sv-parser
- Could integrate with existing SystemVerilog language extensions
- Similar UX to TypeScript’s “Outline” or Java’s “Package Explorer”
User Impact
- Target Users: Hardware engineers, FPGA developers, ASIC designers, verification engineers
- Market: Growing hardware design community using VS Code/Cursor
- Competitive Edge: Would make Cursor a viable alternative to expensive commercial HDL IDEs
Example Workflow
- Open RTL project in Cursor
- Right-click on top module → “Set as Design Top”
- Hierarchy panel populates automatically
- Click any module to jump to its definition
- Expand to see sub-hierarchies
References
- Sigasi Studio hierarchy view
- DVT Eclipse IDE hierarchy browser
- Vivado IDE “Hierarchy” window
- Quartus “Project Navigator”
Operating System (if it applies)
Windows 10/11